1. Technical Field
The present invention relates generally to the semiconductor industry, and more particularly, to the formation of a semiconductor device having reduced planarization defects.
2. Related Art
Planarization processes, such as chemical mechanical polishing (CMP), are often utilized at various stages of semiconductor manufacturing. Unfortunately, these commonly used planarization processes often produce yield detractors or defects, such as scratches, trenches formed by dishing or erosion that create puddles of conductive material, and so on. Often these defects reproduce in subsequent layers of a semiconductor device, resulting in potential shorts, reduced production yields, etc.
Accordingly, there exists a need in the industry for a method of reducing the defects produced during planarization processes.
A first general aspect of the present invention provides a method of forming a semiconductor device, comprising: (a) providing a substrate; (b) depositing a sacrificial layer over a surface of the substrate; (c) forming an at least one interconnection feature within the substrate and the sacrificial layer; (d) depositing a liner within the interconnection feature; (e) depositing a conductive material over the surface of the substrate; (f) planarizing the substrate; and (g) removing the sacrificial layer.
A second general aspect of the present invention provides a method of forming a semiconductor device, comprising: providing a substrate having a first sacrificial layer formed on the substrate; forming at least one first interconnection feature within the substrate and the first sacrificial layer; depositing a first liner within the at least one first interconnection feature; depositing a first conductive material over a surface of the substrate; planarizing the substrate; and removing the first sacrificial layer.
A third general aspect of the present invention provides a method of reducing the formation of defects during semiconductor manufacture, comprising: (a) providing a substrate; (b) depositing a sacrificial layer on the substrate; (c) forming at least one interconnection feature within the sacrificial layer; (d) depositing a conductive material over a surface of the substrate; (e) planarizing the surface of the substrate; and (f) removing the sacrificial layer having defects produced therein from the planarizing.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.